SH7750_08 Datasheet, PDF (557/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Section 13 Bus State Controller (BSC)
Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc
Row
Row
H/L
Row
c1
D63–D0
(read)
BS
CKE
DACKn
(SA: IO → memory)
c1
c2
c3
c4
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.30 Basic Timing for Synchronous DRAM Burst Write
Single Write: The basic timing chart for write access is shown in figure 13.31. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data
is output at the same time as the write command. In the case of a write with auto-precharge,
precharging of the relevant bank is performed in the synchronous DRAM after completion of the
write command, and therefore no command can be issued for synchronous DRAM until
precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a
read access, cycle Trwl is also added as a wait interval until precharging is started following the
write command. Issuance of a new command for synchronous DRAM is postponed during this
Rev.7.00 Oct. 10, 2008 Page 473 of 1074
REJ09B0366-0700