SH7750_08 Datasheet, PDF (261/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
(14) FPU Exception
• Source: Exception due to execution of a floating-point operation
• Transition address: VBR + H'0000 0100
• Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR, and the contents of R15 are saved in SGR. Exception code H'120 is set in EXPEVT.
The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
FPU_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000120;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev.7.00 Oct. 10, 2008 Page 177 of 1074
REJ09B0366-0700