SH7750_08 Datasheet, PDF (349/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Power-Down Modes
9.2.3 Peripheral Module Pin Pull-Up Control
When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins
are pulled up when in the input or high-impedance state.
• Relevant Pins
SCI related pins
DMA related pins
TMU related pin
MD0/SCK
MD7/TXD
RXD
DREQ0
DREQ1
TCLK
MD1/TXD2
MD8/RTS2
CTS2
DACK0
DACK1
MD2/RXD2
SCK2/MRESET
DRAK0
DRAK1
• Other Information
The setting in this register is invalid in the hardware standby mode.
For details of pin states, see Appendix E, Pin Functions.
9.2.4 Standby Control Register 2 (STBCR2)
Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via
the RESET pin or due to watchdog timer overflow.
Bit: 7
6
5
4
3
2
1
0
DSLP STHZ
—
—
—
— MSTP6^* MSTP5^*
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W
R
R
R
R
R/W R/W
Note: * Reserved bit in the SH7750.
Rev.7.00 Oct. 10, 2008 Page 265 of 1074
REJ09B0366-0700