SH7750_08 Datasheet, PDF (365/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9.8.4 In Exit from Deep Sleep Mode
Deep Sleep → Interrupt
Section 9 Power-Down Modes
Interrupt request
CKIO
STATUS Normal
Sleep
Normal
Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence
Deep Sleep → Power-On Reset
Reset
CKIO
RESET^*1
SCK2
STATUS Normal
Sleep
*2
Reset
Normal
0–10 Bcyc
0–30 Bcyc
Notes: 1. When deep sleep mode is exited by means of a power-on reset, hold RESET low for the
oscillation stabilization time.
2. Undefined
Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence
Rev.7.00 Oct. 10, 2008 Page 281 of 1074
REJ09B0366-0700