SH7750_08 Datasheet, PDF(337/1162 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7750_08 Datasheet, PDF (337/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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Section 8 Pipelining

Functional

Category No. Instruction

Instruc-

Execu-

Lock

tion Issue

tion

Group Rate Latency Pattern Stage Start Cycles

System

119 NOP

control

instructions

120

CLRMAC

121 CLRS

MT

1

0

CO

1

3

CO

1

1

#1

â ââ

#28

F1 3

2

#1

â ââ

122 CLRT

MT

1

1

#1

â ââ

123 SETS

CO

1

1

#1

â ââ

124 SETT

MT

1

1

#1

â ââ

125 TRAPA #imm

CO

7

7

#13

â

ââ

126 RTE

CO

5

5

#8

â ââ

127 SLEEP

CO

4

4

#9

â ââ

128 LDTLB

CO

1

1

#2

â ââ

129 LDC

Rm,DBR

CO

1

3

#14

SX 3

2

130 LDC

Rm,GBR

CO

3

3

#15

SX 3

2

131 LDC

Rm,Rp_BANK

CO

1

3

#14

SX 3

2

132 LDC

Rm,SR

CO

4

4

#16

SX 3

2

133 LDC

Rm,SSR

CO

1

3

#14

SX 3

2

134 LDC

Rm,SPC

CO

1

3

#14

SX 3

2

135 LDC

Rm,VBR

CO

1

3

#14

SX 3

2

136 LDC.L @Rm+,DBR

CO

1

1/3

#17

SX 3

2

137 LDC.L @Rm+,GBR

CO

3

3/3

#18

SX 3

2

138 LDC.L @Rm+,Rp_BANK CO

1

1/3

#17

SX 3

2

139 LDC.L @Rm+,SR

CO

4

4/4

#19

SX 3

2

140 LDC.L @Rm+,SSR

CO

1

1/3

#17

SX 3

2

141 LDC.L @Rm+,SPC

CO

1

1/3

#17

SX 3

2

142 LDC.L @Rm+,VBR

CO

1

1/3

#17

SX 3

2

143 LDS

Rm,MACH

CO

1

3

#28

F1 3

2

144 LDS

Rm,MACL

CO

1

3

#28

F1 3

2

145 LDS

Rm,PR

CO

2

3

#24

SX 3

2

146 LDS.L

@Rm+,MACH

CO

1

1/3

#29

F1 3

2

147 LDS.L

@Rm+,MACL

CO

1

1/3

#29

F1 3

2

148 LDS.L

@Rm+,PR

CO

2

2/3

#25

SX 3

2

149 STC

DBR,Rn

CO

2

2

#20

â

ââ

150 STC

SGR,Rn

CO

3

3

#21

â

ââ

Rev.7.00 Oct. 10, 2008 Page 253 of 1074

REJ09B0366-0700

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