SH7750_08 Datasheet, PDF (1051/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
CKIO
BANK
Precharge-sel
Tpr
Tpc
Tr
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3 Td4
t_AD
t_AD
t_AD
Row
t_AD
Row
H/L
Address
Row
c0
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
D63–D0
(write)
BS
t_CSD
t_RWD t_RWD
t_RASD t_RASD t_RASD t_RASD
t_CASD2
t_CASD2
t_CASD2
t_DQMD
t_WDD
CKE
DACKn
(SA: IO ← memory)
t_DACD
t_CSD
t_DQMD
t_RDS
t_RDH
d0
d1
d2
d3
t_WDD
t_BSD t_BSD
t_DACD
t_DACD
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3)
Rev.7.00 Oct. 10, 2008 Page 967 of 1074
REJ09B0366-0700