SH7750_08 Datasheet, PDF (820/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error
interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the
RIE bit is 0.
Bit 3: REIE
Description
0
Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled*
(Initial value)
1
Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled
Note: * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by
reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing
the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will
be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the
interrupt controller is to be notified of ERI and BRI interrupt requests.
Bit 1—Clock Enable 1 (CKE1): Selects the SCIF clock source. The CKE1 bit must be set before
determining the SCIF's operating mode with SCSMR2.
Bit 1: CKE1
Description
0
Internal clock/SCK2 pin functions as port
1
External clock/SCK2 pin functions as clock input*
Note: * Inputs a clock with a frequency 16 times the bit rate.
(Initial value)
Rev.7.00 Oct. 10, 2008 Page 736 of 1074
REJ09B0366-0700