SH7750_08 Datasheet, PDF (669/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
CPU
DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1
CH0
CH1
CH0
CPU
CPU
DMAC channel 1
burst mode
DMAC channel 0 and
channel 1 round robin
mode
Legend:
Priority system: Round robin mode
Channel 0:
Cycle steal mode
Channel 1:
Burst mode (edge-sensing)
DMAC channel 1
burst mode
CPU
Figure 14.11 Bus Handling with Two DMAC Channels Operating
Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
bus is passed to the CPU during a break in requests.
14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising
edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and
DMA transfer executed after four CKIO cycles at the earliest.
When falling edge detection is selected for DREQ, the DMAC will recognize DREQ two cycles
(CKIO) later because the signal must pass through the asynchronous input synchronization circuit.
(There is a 1-cycle (CKIO) delay when low-level detection is selected.)
The second and subsequent DREQ sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer
mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in
the first cycle only, and so DRAK is output in the first cycle only .
Rev.7.00 Oct. 10, 2008 Page 585 of 1074
REJ09B0366-0700