SH7750_08 Datasheet, PDF (225/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
4.6.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed is specified in the address field, and the
longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is
specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry
specification. In RAM mode (CCR.ORA = 1), the OC's data arrays are only accessible in the
memory-mapped cache area, and bit [13] is used to specify the way. For details about address
mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. Address field bits [4:2]
are used for the longword data specification in the entry. As only longword access is used, 0
should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the way and entry set in the address
field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding the way and entry set in
the address field. This write does not set the U bit to 1 on the address array side.
31
24 23
Address field _{1 1 1 1 0 1 0 1}
31
Data field
15 14 13
Way
Longword data
Entry
54 210
L
0
Legend:
L: Longword specification bits
: Reserved bits (0 write value, undefined read value)
Figure 4.15 Memory-Mapped OC Data Array
Rev.7.00 Oct. 10, 2008 Page 141 of 1074
REJ09B0366-0700