SH7750_08 Datasheet, PDF (195/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
Section 4 Caches
4.1 Overview
4.1.1 Features
An SH7750 or SH7750S has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16-
Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) may
alternatively be used as on-chip RAM. The features of this cache are summarized in table 4.1
The SH7750R has an on-chip 16-Kbyte instruction cache (IC) for instructions and 32-Kbyte
operand cache (OC) for data. Half of the memory of the operand cache (16 Kbytes) may
alternatively be used as on-chip RAM. When the EMODE bit of the CCR register is 0, the
SH7750R's cache is set to operate in the SH7750/SH7750S-compatible mode and behaves as
shown in table 4.1. The features of the cache when the EMODE bit in the CCR register is 1 are
given in table 4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset.
For high-speed writing to external memories, this LSI supports 32 bytes × 2 of store queues (SQ).
Table 4.3 lists the features of these SQs.
Table 4.1 Cache Features (SH7750, SH7750S)
Item
Capacity
Instruction Cache
8-Kbyte cache
Type
Line size
Entries
Write method
Direct mapping
32 bytes
256
Operand Cache
16-Kbyte cache or 8-Kbyte cache +
8-Kbyte RAM
Direct mapping
32 bytes
512
Copy-back/write-through selectable
Rev.7.00 Oct. 10, 2008 Page 111 of 1074
REJ09B0366-0700