SH7750_08 Datasheet, PDF (700/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
CMD
TDACK
ID1, ID0
DTR
MD = 10 or 11
CA
D0 D1 D2 D3
WT
Start of data transfer
DTR
MD = 00
CA
D0 D1
WT
Next transfer request
Figure 14.33 Handshake Protocol Using Data Bus
(Channel 0 On-Demand Data Transfer)
Rev.7.00 Oct. 10, 2008 Page 616 of 1074
REJ09B0366-0700