SH7750_08 Datasheet, PDF (825/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 4: BRK
0
Description
A break signal has not been received
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to BRK after reading BRK = 1
(Initial value)
1
A break signal has been received*
[Setting condition]
When data with a framing error is received, followed by the space “0” level
(low level ) for at least one frame length
Note: * When a break is detected, the receive data (H'00) following detection is not transferred
to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive
data transfer is resumed.
Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the
data that is to be read next from SCFRDR2.
Bit 3: FER
0
Description
There is no framing error that is to be read from SCFRDR2 (Initial value)
[Clearing conditions]
• Power-on reset or manual reset
• When there is no framing error in the data that is to be read next from
SCFRDR2
1
There is a framing error that is to be read from SCFRDR2
[Setting condition]
When there is a framing error in the data that is to be read next from
SCFRDR2
Rev.7.00 Oct. 10, 2008 Page 741 of 1074
REJ09B0366-0700