SH7750_08 Datasheet, PDF (691/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Bits 63 to 61: Transmit Size (SZ2–SZ0)
• 000: Byte size (8-bit) specification
• 001: Word size (16-bit) specification
• 010: Longword size (32-bit) specification
• 011: Quadword size (64-bit) specification
• 100: 32-byte block transfer specification
• 101: Setting prohibited
• 110: Request queue clear specification
• 111: Transfer end specification
Bit 60: Read/Write (R/W)
• 0: Memory read specification
• 1: Memory write specification
Bits 59 and 58: Channel Number (ID1, ID0)
• 00: Channel 0 (demand data transfer)
• 01: Channel 1
• 10: Channel 2
• 11: Channel 3
Bits 57 and 56: Transfer Request Mode (MD1, MD0)
• 00: Handshake protocol (data bus used)
• 01: Burst mode (edge detection) specification
• 10: Burst mode (level detection) specification
• 11: Cycle steal mode specification
Bits 55 to 48: Transfer Count (COUNT7–COUNT0)
• Transfer count: 1 to 255
• 00000000: Maximum number of transfers (16M)
Bits 47 to 32: Reserved
Bits 31 to 0: Address (ADDRESS31–ADDRESS0)
• R/W = 0: Transfer source address specification
• R/W = 1: Transfer destination address specification
Notes: 1. Only the ID field is valid for channels 1 to 3.
2. To start DMA transfer by means of demand data transfer on channel 0, the initial value
of MD in the DTR format must be 01, 10, or 11.
Rev.7.00 Oct. 10, 2008 Page 607 of 1074
REJ09B0366-0700