SH7750_08 Datasheet, PDF (176/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 3 Memory Management Unit (MMU)
Instruction access to virtual address (VA)
VA is
VA is
in P4 area in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
Access prohibited
0
CCR.ICE?
1
No
MMUCR.AT = 1
Yes
No
VPNs match
and V = 1
Yes
Search UTLB
Hardware ITLB
miss handling
Match?
No
Yes _{Record in ITLB}
Instruction TLB
miss exception
0
No
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
No
VPNs match
and ASIDs match and
V=1
Yes
Only one
No
entry matches
Yes
0 (User)
PR?
1
SR.MD?
1 (Privileged)
Instruction TLB
multiple hit exception
Instruction TLB protection
violation exception
C=1
No
and CCR.ICE = 1
Yes
Cache access
Memory access
(Non-cacheable)
Figure 3.11 Flowchart of Memory Access Using ITLB
Rev.7.00 Oct. 10, 2008 Page 92 of 1074
REJ09B0366-0700