SH7750_08 Datasheet, PDF (655/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
• Usage Notes
An external request (DREQ) is detected by a low level or falling edge. Ensure that the external
request (DREQ) signal is held high when there is no DMA transfer request from an external
device after a power-on reset or manual reset.
When DMA transfer is restarted, check whether a DMA transfer request is being held.
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to
a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in
table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit
(TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the
two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input.
The source of the transfer request does not have to be the data transfer source or destination.
However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full
interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2).
When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty
interrupt), the transfer destination must be the SCI/SCIF's transmit data register
(SCTDR1/SCFTDR2).
Rev.7.00 Oct. 10, 2008 Page 571 of 1074
REJ09B0366-0700