SH7750_08 Datasheet, PDF (644/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For channel 0, in DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the DTR
format.
Bit 13: SM1
0
1
Bit 12: SM0
0
1
0
1
Description
Source address fixed
(Initial value)
Source address incremented (+1 in 8-bit transfer, +2 in 16-bit
transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
Source address decremented (–1 in 8-bit transfer, –2 in 16-bit
transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32-
byte burst transfer)
Setting prohibited
Rev.7.00 Oct. 10, 2008 Page 560 of 1074
REJ09B0366-0700