SH7750_08 Datasheet, PDF (298/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Instruction Set
Addressing Instruction
Mode
Format
PC-relative disp:12
Effective Address Calculation Method
Calculation
Formula
Effective address is PC+4 with 12-bit displacement PC + 4 + disp
disp added after being sign-extended and
× 2 → Branch-
multiplied by 2.
Target
PC
+
4
+
disp
(sign-extended)
×
PC + 4 + disp × 2
2
Rn
Effective address is sum of PC+4 and Rn.
PC + 4 + Rn
→ Branch-
PC
Target
+
4
+
PC + 4 + Rn
Rn
Immediate #imm:8
8-bit immediate data imm of TST, AND, OR, or
—
XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or
—
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction is —
zero-extended and multiplied by 4.
Note:
For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the chip. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative
Rev.7.00 Oct. 10, 2008 Page 214 of 1074
REJ09B0366-0700