SH7750_08 Datasheet, PDF (351/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Power-Down Modes
9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
Clock-stop register 00 (CLKSTP00) controls the operation clock for peripheral modules. To
resume supply of the clock signal, write a 1 to the corresponding bit in the CLKSTPCLR00
register. Writing a 0 to the CLKSTP00 register does not affect the register's value. The
CLKSTP00 register is a 32-bit register that can be read from or written to. It is initialized to
H'0000 0000 by a power-on reset, but not by a manual reset or when the device enters standby
mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — — — — — — — — — — CSTP1 CSTP0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R/W R/W
Bits 31 to 2—Reserved: Any data written to these bits should always be 0. These bits are always
read as 0.
Bit 1—Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to
channels 3 and 4 of the timer unit (TMU).
Bit 1: CSTP1
0
1
Description
Peripheral clock is supplied to TMU channels 3 and 4
(Initial value)
Peripheral clock supply to TMU channels 3 and 4 is stopped
Bit 0⎯Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt
controller (INTC). If this bit is set, INTC does not detect interrupts on the TMU's channels 3 and
4.
Bit 0: CSTP0
0
1
Description
INTC detects interrupts on channels 3 and 4 of the TMU (Initial value)
INTC does not detect interrupts on channels 3 and 4 of the TMU
Rev.7.00 Oct. 10, 2008 Page 267 of 1074
REJ09B0366-0700