SH7750_08 Datasheet, PDF (89/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 1 Overview
Item
Features
Cache memory
• Instruction cache (IC)
[SH7750, SH7750S] _{⎯ 8 Kbytes, direct mapping}
⎯ 256 entries, 32-byte block length
⎯ Normal mode (8-Kbyte cache)
⎯ Index mode
• Operand cache (OC)
⎯ 16 Kbytes, direct mapping
⎯ 512 entries, 32-byte block length
⎯ Normal mode (16-Kbyte cache)
⎯ Index mode
⎯ RAM mode (8-Kbyte cache + 8-Kbyte RAM)
⎯ Choice of write method (copy-back or write-through)
• Single-stage copy-back buffer, single-stage write-through buffer
• Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
• Store queue (32 bytes × 2 entries)
Cache memory
[SH7750R]
• Instruction cache (IC)
⎯ 16 Kbytes, 2-way set associative
⎯ 256 entries/way, 32-byte block length
⎯ Cache-double-mode (16-Kbyte cache)
⎯ Index mode
⎯ SH7750/SH7750S-compatible mode (8 Kbytes, direct mapping)
• Operand cache (OC)
⎯ 32 Kbytes, 2-way set associative
⎯ 512 entries/way, 32-byte block length
⎯ Cache-double-mode (32-Kbyte cache)
⎯ Index mode
⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM)
⎯ SH7750/SH7750S-compatible mode (16 Kbytes, direct mapping)
• Single-stage copy-back buffer, single-stage write-through buffer
• Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
• Store queue (32 bytes × 2 entries)
Rev.7.00 Oct. 10, 2008 Page 5 of 1074
REJ09B0366-0700