SH7750_08 Datasheet, PDF (267/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
4. An exception must not be generated in an RTE instruction delay slot, as the operation will be
undefined in this case.
5.8 Restrictions
1. Restrictions on first instruction of exception handling routine
• Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR
+ H'400, or VBR + H'600.
• When the UBDE bit in the BRCR register is set to 1 and the user break debug support
function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address
indicated by the DBR register.
Note: * See section 20.4, User Break Debug Support Function.
Rev.7.00 Oct. 10, 2008 Page 183 of 1074
REJ09B0366-0700