SH7750_08 Datasheet, PDF (564/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tncp Tnop Tc1 Tc2 Tc3 Tc4 Trwl Trwl
Row
H/L
c1
D63–D0
(read)
BS
CKE
c1
c2
c3
c4
Single-address DMA
DACKn
(SA: IO → memory)
Normal write
Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as
shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal
is output as shown by the dotted line. DACKn shows an example where DMAC, CHCRn,
and AL (acknowledge level) are 0.
Figure 13.36 Burst Write Timing (Same Row Address)
Rev.7.00 Oct. 10, 2008 Page 480 of 1074
REJ09B0366-0700