SH7750_08 Datasheet, PDF (444/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
13.1.3 Pin Configuration
Table 13.1 shows the BSC pin configuration.
Table 13.1 BSC Pins
Name
Address bus
Data bus
Signals
A25−A0
D63−D52,
D31−D0
Data bus/port
Bus cycle start
D51−D32/
PORT19−
PORT0
BS
Chip select 6−0 CS6−CS0
Read/write
RD/WR
Row address
strobe
Read/column
address strobe/
cycle frame
RAS
RD/CASS/
FRAME
I/O Description
O
Address output
I/O Data input/output
When port functions are used and DDT mode is
selected, input the DTR format. Otherwise, when
port functions are used, D63−D52 cannot be used
and should be left open.
I/O When port functions are not used: data input/output
When port functions are used: input/output port
(input or output set for each bit by register)
O
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface:
asserted once for a burst transfer
For other burst transfers: asserted each data cycle
O
Chip select signals that indicate the area being
accessed
CS5 and CS6 are also used as PCMCIA CE1A and
CE1B
O
Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
O
RAS signal when setting DRAM/synchronous DRAM
interface
O
Strobe signal that indicates a read cycle
When setting synchronous DRAM interface: CAS
signal
When setting MPX interface: FRAME signal
Rev.7.00 Oct. 10, 2008 Page 360 of 1074
REJ09B0366-0700