SH7750_08 Datasheet, PDF (311/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Instruction Set
Table 7.12 Floating-Point Graphics Acceleration Instructions
Instruction
FMOV DRm,XDn
FMOV XDm,DRn
FMOV XDm,XDn
FMOV @Rm,XDn
FMOV @Rm+,XDn
FMOV @(R0,Rm),XDn
FMOV XDm,@Rn
FMOV XDm,@-Rn
FMOV XDm,@(R0,Rn)
FIPR FVm,FVn
FTRV XMTRX,FVn
FRCHG
FSCHG
Operation
Instruction Code
Privileged T Bit
DRm → XDn
1111nnn1mmm01100 —
—
XDm → DRn
1111nnn0mmm11100 —
—
XDm → XDn
1111nnn1mmm11100 —
—
(Rm) → XDn
1111nnn1mmmm1000 —
—
(Rm) → XDn, Rm + 8 → Rm 1111nnn1mmmm1001 —
—
(R0 + Rm) → XDn
1111nnn1mmmm0110 —
—
XDm → (Rn)
1111nnnnmmm11010 —
—
Rn – 8 → Rn, XDm → (Rn)
1111nnnnmmm11011 —
—
XDm → (R0+Rn)
1111nnnnmmm10111 —
—
inner_product [FVm, FVn] → 1111nnmm11101101 —
—
FR[n+3]
transform_vector [XMTRX, FVn] 1111nn0111111101 —
—
→ FVn
~FPSCR.FR → FPSCR.FR 1111101111111101 —
—
~FPSCR.SZ → FPSCR.SZ 1111001111111101 —
—
7.4 Usage Notes
7.4.1
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction
(H'FFFD)
• Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction
code H'FFFD is executed.
• The ITLB hit judgment may be incorrect when a TRAPA instruction or undefined instruction
code H'FFFD is executed, causing a multi-hit exception to occur after re-registration.
• Incorrect data may be written to an FPU-related register or to the MACH or MACL register
when a TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is
executed.
Conditions Under which Problem Occurs
1. Incorrect data may be written to the instruction cache when the following three conditions
occur at the same time.
a. The instruction cache is enabled (CCR.ICE = 1).
Rev.7.00 Oct. 10, 2008 Page 227 of 1074
REJ09B0366-0700