SH7750_08 Datasheet, PDF (550/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Byte specification is performed by DQM0 to DQM7. A read/write is performed for the byte for
which the corresponding DQM signal is low. When the bus width is 64 bits, in big-endian mode
DQM7 specifies an access to address 8n, and DQM0 specifies an access to address 8n + 7. In
little-endian mode, DQM7 specifies an access to address 8n + 7, and DQM0 specifies an access to
address 8n.
Figures 13.26 and 13.27 show examples of the connection of 16M × 16-bit synchronous DRAMs.
SH7750, SH7750S, SH7750R
A12–A3
CKIO
CKE
CS3
RAS
CASS
RD/WR
D63–D48
DQM7
DQM6
512K × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
D47–D32
DQM5
DQM4
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
D31–D16
DQM3
DQM2
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
D15–D0
DQM1
DQM0
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)
Rev.7.00 Oct. 10, 2008 Page 466 of 1074
REJ09B0366-0700