SH7750_08 Datasheet, PDF (638/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 32-bit readable/writable registers
that specify the transfer count for the corresponding channel (byte count, word count, longword
count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while
H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the
remaining number of transfers is shown.
Bits 31–24 of these registers are reserved; they are always read as 0, and should only be written
with 0.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode and deep sleep mode.
In DDT mode, settings to DMATCR0[7:0] may be made from DTR format [55:48] as well. For
details, see Data Transfer Request Format in section 14.5.2, Pin in DDT Mode.
Rev.7.00 Oct. 10, 2008 Page 554 of 1074
REJ09B0366-0700