SH7750_08 Datasheet, PDF (15/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
9.7.2 Exit from
Hardware Standby
Mode
Page
274
9.7.3 Usage Notes 275
9.8.1 In Reset
276
Figure 9.2 STATUS
Output in Manual Reset
Revision (See Manual for Details)
Description amended
Setting the CA pin level high after the RESET pin level has
been set low and the SCK2 pin high starts the clock to oscillate.
The RESET pin level should be kept low until the clock has
stabilized, then set high so that the CPU starts the power-on
reset exiting procedure.
Description amended
1. The CA pin level must be kept high when the RTC power
supply is started (figure 9.15).
2. On the SH7750R, power must be supplied to the other power
supply
pins
(V ,
DD
V,
DDQ
V , _DD−CPG
V , _DD−PLL1
and
V_DD−PLL2),
in
addition
to the RTC power supply pin, in hardware standby mode.
Figure amended
CKIO
RESET^*
Must be asserted for
t_RESW or longer
SCK2
9.8.5 Hardware
285
Standby Mode Timing
(SH7750S, SH7750R
Only)
Figure 9.15 Timing
When VDD-RTC Power
is Off → On
STATUS Normal
Reset
Normal
≥ 0 Bcyc
0–30 Bcyc
Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting
until the end of the currently executing bus cycle.
Figure amended
V_DD-RTC
CA
Power-on oscillation
setting time
V_DD, V_DDQ*
RESET
Min 0s
9.9 Usage Notes
286
SCK2
Note: * V_DD, V_DD-PLL1/2, V_DDQ, V_DD-CPG
Newly added
Rev.7.00 Oct. 10, 2008 Page xv of lxxxiv
REJ09B0366-0700