SH7750_08 Datasheet, PDF (196/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
Table 4.2 Cache Features (SH7750R)
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Instruction Cache
Operand Cache
16-Kbyte cache
32-Kbyte cache or 16-Kbyte cache +
16-Kbyte RAM
2-way set-associative
2-way set-associative
32 bytes
32 bytes
256 entries/way
512 entries/way
Copy-back/write-through selectable
LRU (least-recently-used) algorithm LRU algorithm
Table 4.3 Features of Store Queues
Item
Capacity
Addresses
Write
Write-back
Access right
Store Queues
2 × 32 bytes
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
Rev.7.00 Oct. 10, 2008 Page 112 of 1074
REJ09B0366-0700