SH7750_08 Datasheet, PDF (1091/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
Table 22.34 Peripheral Module Signal Timing (3)
HD6417750S
VF133 (V)
HD6417750S
VBT133 (V)
*²
HD6417750
SF167 (V)
HD6417750
SF200 (V)
*³
HD6417750
SBP200 (V)
*⁴
Module Item
INTC
NMI pulse
width (high)
NMI pulse
width (low)
H-UDI Input clock
cycle
Symbol
t
NMIH
t
NMIL
t_TCKcyc
Min
5
30
5
30
50
Max
—
—
—
—
—
Min Max
5
—
30 —
5
—
30 —
50 —
Min Max Unit
5
—t
cyc
30 — ns
5
—t
cyc
30 — ns
50 — ns
Figure
22.71 Normal or sleep mode
22.71 Standby mode
22.71 Normal or sleep mode
22.71 Standby mode
22.67
Input clock t
TCKH
pulse width
(high)
Input clock t
TCKL
pulse width
(low)
Input clock t
TCKr
rise time
15 —
15 —
15 — ns
22.67
15 —
15 —
15 — ns
22.67
— 10
— 10
— 10 ns
22.67
Input clock fall t
TCKf
time
ASEBRK
setup time
t_ASEBRKS
ASEBRK hold t_ASEBRKH
time
TDI/TMS
t
TDIS
setup time
TDI/TMS hold t
TDIH
time
— 10
10 —
10 —
15 —
15 —
— 10
10 —
10 —
15 —
15 —
— 10 ns
10
—
t_cyc
10
—
t_cyc
15 — ns
15 — ns
22.67
22.68
22.68
22.69
22.69
TDO delay t
TDO
time
0
10
0
10
0
10 ns
22.69
ASE-PINBRK t_PINBRK
pulse width
2
—
2
—
2
— Pcyc^*1 22.70
Notes: 1. Pcyc: P clock cycles
2. V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to +75°C, C_L = 30 pF, PLL2 on
3. V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –20 to +75°C, C_L = 30 pF, PLL2 on
4. V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –20 to +75°C, C_L = 30 pF, PLL2 on
Rev.7.00 Oct. 10, 2008 Page 1007 of 1074
REJ09B0366-0700