SH7750_08 Datasheet, PDF (658/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Transfer on channel 0
Initial priority order CH0 > CH1 > CH2 > CH3
Channel 0 is given the lowest
priority.
Priority order after transfer CH1 > CH2 > CH3 > CH0
Transfer on channel 1
Initial priority order CH0 > CH1 > CH2 > CH3
Priority order after transfer ^{CH2 > CH3 > CH0 > CH1}
When channel 1 is given the
lowest priority, the priority of
channel 0, which was higher
than channel 1, is also
shifted simultaneously.
Transfer on channel 2
Initial priority order CH0 > CH1 > CH2 > CH3
When channel 2 is given the
lowest priority, the priorities of
channels 0 and 1, which were
higher than channel 2, are
also shifted simultaneously. If
there is a transfer request for
channel 1 only immediately
Priority order after transfer CH3 > CH0 > CH1 > CH2 _{afterward, channel 1 is given}
the lowest priority and the
priorities of channels 3 and 0
are simultaneously shifted
Priority after transfer due to
issuance of a transfer request
down.
CH2 > CH3 > CH0 > CH1
for channel 1 only.
Transfer on channel 3
Initial priority order _{CH0 > CH1 > CH2 > CH3}
No change in priority order
Priority order after transfer CH0 > CH1 > CH2 > CH3
Figure 14.3 Round Robin Mode
Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The
operation of the DMAC in this case is as follows.
Rev.7.00 Oct. 10, 2008 Page 574 of 1074
REJ09B0366-0700