SH7750_08 Datasheet, PDF (1022/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 22 Electrical Characteristics
Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V))
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to +75°C, C_L = 30 pF
Item
Symbol Min
EXTAL
PLL2
1/2 divider
f_EX
16
clock input operating operating
frequency
1/2 divider not f
8
EX
operating
PLL2
1/2 divider
f
2
EX
not
operating
operating _{1/2 divider not fEX}
1
operating
EXTAL clock input cycle time
t_EXcyc
23
EXTAL clock input low-level pulse width t
3.5
EXL
EXTAL clock input high-level pulse width t_EXH
3.5
EXTAL clock input rise time
t
—
EXr
EXTAL clock input fall time
t
—
EXf
CKIO clock PLL2 operating
f
25
OP
output
PLL2 not operating
f_OP
1
CKIO clock output cycle time
t_cyc
15
CKIO clock output low-level pulse width t_CKOL1
1
CKIO clock output high-level pulse width t_CKOH1
1
CKIO clock output rise time
t
—
CKOr
CKIO clock output fall time
t_CKOf
—
CKIO clock output low-level pulse width t
3
CKOL2
CKIO clock output high-level pulse width t
3
CKOH2
Power-on oscillation settling time
t
10
OSC1
Power-on oscillation settling time/mode t_OSCMD
10
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
RESET assert time
t_SCK2RS
20
t_SCK2RH
20
t
3
MDRS
t_MDRH
20
t
20
RESW
Max Unit Figure
43
MHz
22
43
22
1000
—
—
4
4
64
64
1000
—
—
3
3
—
—
—
—
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
22.1
22.1
22.1
22.1
22.1
22.2 (1)
22.2 (1)
22.2 (1)
22.2 (1)
22.2 (1)
22.2 (2)
22.2 (2)
22.3, 22.5
22.3, 22.5
—
ns 22.11
—
ns 22.3, 22.5, 22.11
—
t
22.12
cyc
—
ns 22.3, 22.5, 22.12
—
t
22.3, 22.4, 22.5,
cyc
22.6, 22.11
Rev.7.00 Oct. 10, 2008 Page 938 of 1074
REJ09B0366-0700