SH7750_08 Datasheet, PDF (711/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
RAS,
CAS, WE
TDACK
RA
CA
D0 D1 D2 D3 D4 D5 D6 D7
BA
RD
ID1, ID0
10
No DTR cycle, so requests can be made at any time
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/
External Bus → External Device Data Transfer/
Direct Data Transfer Request to Channel 2 without Using Data Bus
Rev.7.00 Oct. 10, 2008 Page 627 of 1074
REJ09B0366-0700