SH7750_08 Datasheet, PDF (649/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 14 Direct Memory Access Controller (DMAC)
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
Description
0
Normal DMA mode
(Initial value)
1
On-demand data transfer mode
Note: BAVL (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
the BAVL pin function is enabled and this pin becomes an active-low output.
Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
Bit 9: PR1
0
1
Bit 8: PR0
0
1
0
1
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round robin mode
(Initial value)
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4 (SH7750S)—Check Overrun for DREQ (COD): When this bit is set to 1, cancellation of
an accepted DREQ acceptance flag is enabled. When cancellation of an accepted DREQ
acceptance flag is enabled by setting COD to 1, clear CHCRn.DS to 0 and then negate DREQ (to
the high level). For details, see External Request Mode in section 14.3.2, DMA Transfer Requests.
Bit 4: COD
Description
0
DREQ acceptance flag cancellation disabled
(Initial value)
1
DREQ acceptance flag cancellation enabled
Note: When external request mode is used in the SH7750S, recommend setting COD to 1
permanently.
Bit 4 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
Rev.7.00 Oct. 10, 2008 Page 565 of 1074
REJ09B0366-0700