SH7750_08 Datasheet, PDF (301/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Instruction Set
Instruction
Operation
MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn
MOV.B R0,@(disp,GBR) R0 → (disp + GBR)
MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR)
MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR)
MOV.B
@(disp,GBR),R0 (disp + GBR) →
sign extension → R0
MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →
sign extension → R0
MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0
MOVA
@(disp,PC),R0
disp × 4 + PC & H'FFFFFFFC
+ 4 → R0
MOVT Rn
T → Rn
SWAP.B Rm,Rn
Rm → swap lower 2 bytes
→ Rn
SWAP.W Rm,Rn
Rm → swap upper/lower
words → Rn
XTRCT Rm,Rn
Rm:Rn middle 32 bits → Rn
Instruction Code
Privileged
0000nnnnmmmm1110 —
11000000dddddddd —
11000001dddddddd —
11000010dddddddd —
11000100dddddddd —
11000101dddddddd —
11000110dddddddd —
11000111dddddddd —
0000nnnn00101001 —
0110nnnnmmmm1000 —
0110nnnnmmmm1001 —
0010nnnnmmmm1101 —
T Bit
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Rev.7.00 Oct. 10, 2008 Page 217 of 1074
REJ09B0366-0700