SH7750_08 Datasheet, PDF (853/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.12 shows an example of the operation when modem control is used.
Serial data
RxD2
Start
bit
0 D0 D1 D2
Parity Stop
bit bit
D7 0/1 1
Start
bit
0
RTS2
Figure 16.12 Example of Operation Using Modem Control (RTS2)
16.4 SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receive-
error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt
(BRI) request.
Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When transmission/reception is carried out using the DMAC, output of interrupt requests to the
interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE
bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but
not RXI interrupt requests.
When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty
request is generated separately from the interrupt request. A transmit-FIFO-data-empty request can
activate the DMAC to perform data transfer.
When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is
generated separately from the interrupt request. A receive-FIFO-data-full request can activate the
DMAC to perform data transfer.
When using the DMAC for transmission/reception, set and enable the DMAC before making the
SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the
DMAC setting procedure.
Rev.7.00 Oct. 10, 2008 Page 769 of 1074
REJ09B0366-0700