SH7750_08 Datasheet, PDF (381/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Clock Oscillation Circuits
Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 5: BFC2
0
Bit 4: BFC1
0
1
1
0
Other than the above
Bit 3: BFC0
0
1
0
1
0
1
Description
×1
×1/2
×1/3
×1/4
×1/6
×1/8
Setting prohibited (Do not set)
Bits 2 to 0—Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the
peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency
divider, or PLL circuit 1 output frequency.
Bit 2: PFC2
0
Bit 1: PFC1
0
1
1
0
Other than the above
Bit 0: PFC0
0
1
0
1
0
Description
×1/2
×1/3
×1/4
×1/6
×1/8
Setting prohibited (Do not set)
Rev.7.00 Oct. 10, 2008 Page 297 of 1074
REJ09B0366-0700