SH7750_08 Datasheet, PDF (469/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

T1
Tw
CKIO
RDY
(BCR4.ASYNC0 = 0)
Section 13 Bus State Controller (BSC)
Tw
Twe
T2
RDY
(BCR4.ASYNC0 = 1)
Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set
(Two Wait Cycles Are Inserted by WCR2)
Rev.7.00 Oct. 10, 2008 Page 385 of 1074
REJ09B0366-0700