SH7750_08 Datasheet, PDF (450/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
Table 13.3 External Memory Space Map
Area
External
Addresses
Size
Connectable
Memory
Settable Bus
Widths
Access Size
0
H'00000000–
64 Mbytes SRAM
H'03FFFFFF
Burst ROM
MPX
8, 16, 32, 64^*1
8, 16, 32^*1, 64^*7
32, 64^*1
8, 16, 32,
64^*6 bits,
32 bytes
1
H'04000000–
64 Mbytes SRAM
8, 16, 32, 64^*2 8, 16, 32,
H'07FFFFFF
MPX
32, 64^*2
Byte control SRAM 16, 32, 64^*2
64^*6 bits,
32 bytes
2
H'08000000–
64 Mbytes SRAM
8, 16, 32, 64^*2 8, 16, 32,
H'0BFFFFFF
Synchronous DRAM 32, 64^{*2 *3}
DRAM
16, 32^{*2 *3}
64^*6 bits,
32 bytes
MPX
32, 64^*2
3
H'0C000000– 64 Mbytes SRAM
8, 16, 32, 64^*2 8, 16, 32,
H'0FFFFFFF
Synchronous DRAM 32, 64^{*2 *3}
DRAM
16, 32, 64^{*2 *3}
64^*6 bits,
32 bytes
MPX
32, 64^*2
4
H'10000000–
64 Mbytes SRAM
8, 16, 32, 64^*2 8, 16, 32,
H'13FFFFFF
MPX
Byte control RAM
32, 64^*2
16, 32, 64^*2
64^*6 bits,
32 bytes
5
H'14000000–
64 Mbytes SRAM
H'17FFFFFF
MPX
Burst ROM
8, 16, 32, 64^*2
32, 64^*2
8, 16, 32^*2, 64^*7
8, 16, 32,
64^*6 bits,
32 bytes
PCMCIA
6
H'18000000–
64 Mbytes SRAM
H'1BFFFFFF
MPX
Burst ROM
8, 16^{*2 *4}
8, 16, 32, 64^*2
32, 64^*2
8,16, 32^*2, 64^*7
8, 16, 32,
64^*6 bits,
32 bytes
PCMCIA
7^*5
H'1C000000– 64 Mbytes —
H'1FFFFFFF
8,16^{*2 *4}
—
Notes: 1. Memory bus width specified by external pins
2. Memory bus width specified by register
3. With synchronous DRAM interface, bus width is 32 or 64 bits only.
With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits
only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by
MCR.
4. With PCMCIA interface, bus width is 8 or 16 bits only.
5. Do not access a reserved area, as operation cannot be guaranteed in this case.
Rev.7.00 Oct. 10, 2008 Page 366 of 1074
REJ09B0366-0700