SH7750_08 Datasheet, PDF (253/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
(6) Data Address Error
• Sources:
⎯ Word data access from other than a word boundary (2n +1)
⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)
⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n
+ 4, 8n + 5, 8n + 6, or 8n + 7)
⎯ Access to area H'8000 0000–H'FFFF FFFF in user mode
• Transition address: VBR + H'0000 0100
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR, and the contents of R15 are saved in SGR.
Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For
details, see section 3, Memory Management Unit (MMU).
Data_address_error()
{
TEA = EXCEPTION_ADDRESS;
PTEN.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access? H'000000E0: H'00000100;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev.7.00 Oct. 10, 2008 Page 169 of 1074
REJ09B0366-0700