SH7750_08 Datasheet, PDF (555/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc
Row
Row
H/L
Row
c1
c1
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.29 Basic Timing for Synchronous DRAM Single Read
Rev.7.00 Oct. 10, 2008 Page 471 of 1074
REJ09B0366-0700