SH7750_08 Datasheet, PDF (806/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 15 Serial Communication Interface (SCI)
• When using the DMAC for transmission/reception, making a setting to disable RXI and TXI
interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set,
interrupt requests to the interrupt controller will be cleared by the DMAC independently of the
interrupt handling program.
When Using Synchronous External Clock Mode:
• Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
SCK has changed from 0 to 1.
• Only set both TE and RE to 1 when external clock SCK is 1.
• In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles
after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to
SCRDR1 will not be possible.
When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero
1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF
will be set to 1 but copying to SCRDR1 will not be possible.
When Using DMAC: When using the DMAC for transmission/reception, make a setting to
suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is
made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by
the DMAC independently of the interrupt handling program.
SH7750 Only: When the following conditions are satisfied, the same data may be transmitted
multiple times.
• Conditions Under which Problem Occurs
a. External SCK clock input mode is selected (SCSCR1.CKE1 = 1).
b. Synchronous mode is selected (SCSMR1C/A = 1).
c. Transmit or receive is in progress (SCSCR1.TE = 1).
Conditions a. to c. must all be satisfied.
• Workarounds
Workaround 1
⎯ PLL2 on
As shown in figure 15.26, after synchronizing asynchronous input external clock SCK with
CKIO, input it to the SCK pin of the SH7750. In this case the SCK clock cycle minimum
value will be: peripheral clock cycle (Pck) × 8. Note that this workaround will reduce the
timing margins of the TxD and RxD pins synchronized with the SCK pin.
⎯ PLL2 off
Operation cannot be guaranteed. (Usage prohibited.)
Rev.7.00 Oct. 10, 2008 Page 722 of 1074
REJ09B0366-0700