SH7750_08 Datasheet, PDF (916/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Interrupt Controller (INTC)
will secure the necessary timing internally. When updating a number of flags, there is no problem
if only the register containing the last flag updated is read.
If flag updating is performed while the BL bit is cleared to 0, the program may jump to the
interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is
initiated due to the timing relationship between the flag update and interrupt request recognition
within the chip. Processing can be continued without any problem by executing an RTE
instruction.
19.2.4 Interrupt Exception Handling and Priority
Table 19.5 lists the codes for the interrupt event register (INTEVT), and the order of interrupt
priority. Each interrupt source is assigned a unique INTEVT code. The start address of the
interrupt handler is common to each interrupt source. This is why, for instance, the value of
INTEVT is used as an offset at the start of the interrupt handler and branched to in order to
identify the interrupt source.
The order of priority of the on-chip peripheral modules is specified as desired by setting priority
levels from 0 to 15 in interrupt priority registers A to D (IPRA–IPRD). The order of priority of the
on-chip peripheral modules is set to 0 by a reset.
When the priorities for multiple interrupt sources are set to the same level and such interrupts are
generated simultaneously, they are handled according to the default priority order shown in table
19.5.
Updating of interrupt priority registers A to D, 00 should only be carried out when the BL bit in
the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read one of the
interrupt priority registers, then clear the BL bit to 0. This will secure the necessary timing
internally.
Rev.7.00 Oct. 10, 2008 Page 832 of 1074
REJ09B0366-0700