SH7750_08 Datasheet, PDF (214/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Caches
• Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
• LRU (SH7750R only)
In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be
registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware.
The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently
accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.
The LRU bits cannot be read or written by software.
4.4.2 Read Operation
When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
• If the tag matches and the V bit is 1
→ (3a)
• If the tag matches and the V bit is 0
→ (3b)
• If the tag does not match and the V bit is 0 → (3b)
• If the tag does not match and the V bit is 1 → (3b)
3a. Cache hit
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
3b. Cache miss
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
Rev.7.00 Oct. 10, 2008 Page 130 of 1074
REJ09B0366-0700