SH7750_08 Datasheet, PDF (275/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 Floating-Point Unit (FPU)
6.3.2 Floating-Point Status/Control Register (FPSCR)
Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)
31
22 21 20 19 18 17
12 11
76
—
FR SZ PR DN
Cause
Enable
Flag
Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
210
RM
• FR: Floating-point register bank
FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–
FPR15_BANK1 are assigned to XF0–XF15.
FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–
FPR15_BANK1 are assigned to FR0–FR15.
• SZ: Transfer size mode
SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
• PR: Precision mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (graphics
support instructions are undefined).
Do not set SZ and PR to 1 simultaneously; this setting is reserved.
[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
• DN: Denormalization mode
DN = 0: A denormalized number is treated as such.
DN = 1: A denormalized number is treated as zero.
• Cause: FPU exception cause field
• Enable: FPU exception enable field
Rev.7.00 Oct. 10, 2008 Page 191 of 1074
REJ09B0366-0700