SH7750_08 Datasheet, PDF (67/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding
Burst Read Cycle.................................................................................................... 483
Figure 13.39 Auto-Refresh Operation ......................................................................................... 485
Figure 13.40 Synchronous DRAM Auto-Refresh Timing........................................................... 486
Figure 13.41 Synchronous DRAM Self-Refresh Timing ............................................................ 487
Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ........................................ 490
Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set)..................... 491
Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4).................. 492
Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM......................................... 494
Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width
(256 Mbits)............................................................................................................. 495
Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width
(TRAS[2:0] = 001, TRC[2:0] = 001)...................................................................... 496
Figure 13.47 Burst ROM Basic Access Timing .......................................................................... 498
Figure 13.48 Burst ROM Wait Access Timing ........................................................................... 499
Figure 13.49 Burst ROM Wait Access Timing ........................................................................... 500
Figure 13.50 Example of PCMCIA Interface .............................................................................. 504
Figure 13.51 Basic Timing for PCMCIA Memory Card Interface .............................................. 505
Figure 13.52 Wait Timing for PCMCIA Memory Card Interface ............................................... 506
Figure 13.53 PCMCIA Space Allocation .................................................................................... 507
Figure 13.54 Basic Timing for PCMCIA I/O Card Interface ...................................................... 508
Figure 13.55 Wait Timing for PCMCIA I/O Card Interface ....................................................... 509
Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 510
Figure 13.57 Example of 64-Bit Data Width MPX Connection.................................................. 512
Figure 13.58 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait,
Bus Width: 64 Bits)................................................................................................ 513
Figure 13.59 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted,
Bus Width: 64 Bits)................................................................................................ 514
Figure 13.60 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait,
Bus Width: 64 Bits)................................................................................................ 515
Figure 13.61 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted,
Bus Width: 64 Bits)................................................................................................ 516
Figure 13.62 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait,
Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... 517
Figure 13.63 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control,
Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... 518
Figure 13.64 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait,
Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... 519
Figure 13.65 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control,
Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... 520
Rev.7.00 Oct. 10, 2008 Page lxvii of lxxxiv
REJ09B0366-0700