SH7750_08 Datasheet, PDF (317/1162 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Pipelining
1. 1-step operation: 1 issue cycle
EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*,
DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#,
ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT,
LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS,
single-/double-precision FABS/FNEG
I
D
EX
NA
S
2. Load/store: 1 issue cycle
MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR
I
D
EX
MA
S
3. GBR-based load/store: 1 issue cycle
MOV.[BWL]@(d,GBR)
I
D
SX
MA
S
4. JMP, RTS, BRAF: 2 issue cycles
I
D
EX
NA
S
D
EX
NA
S
5. TST.B: 3 issue cycles
I
D
SX
MA
S
D
SX
NA
S
D
SX
NA
S
6. AND.B, OR.B, XOR.B: 4 issue cycles
I
D
SX
MA
S
D
SX
NA
S
D
SX
NA
S
D
SX
MA
S
7. TAS.B: 5 issue cycles
I
D
EX
MA
S
D
EX
MA
S
D
EX
NA
S
D
EX
NA
S
D
EX
MA
S
8. RTE: 5 issue cycles
I
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
9. SLEEP: 4 issue cycles
I
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
Figure 8.2 Instruction Execution Patterns
Rev.7.00 Oct. 10, 2008 Page 233 of 1074
REJ09B0366-0700