PIC16LF18854 Datasheet, PDF (93/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2: SUPERVISORS
R/P-1
DEBUG
bit 13
R/P-1
STVREN
R/P-1
PPS1WAY
R/P-1
ZCDDIS
R/P-1
BORV
U-1
—
bit 8
R/P-1
R/P-1
R/P-1
U-1
U-1
U-1
R/P-1
R/P-1
BOREN<1:0>
LPBOREN
—
—
—
PWRTE
MCLRE
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
n = Value when blank or after Bulk Erase
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4-2
bit 1
bit 0
DEBUG: Debugger Enable bit⁽²⁾
1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins
0 = ON
Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON
Stack Overflow or Underflow will cause a Reset
0 = OFF Stack Overflow or Underflow will not cause a Reset
PPS1WAY: PPSLOCKED One-Way Set Enable bit
1 = ON
The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
0 = OFF The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
ZCDDIS: Zero-Cross Detect Disable bit
1 = ON
ZCD disabled. ZCD can be enabled by setting the EN bit of the ZCDxCON register
0 = OFF
ZCD always enabled (EN bit is ignored)
BORV: Brown-out Reset Voltage Selection bit⁽¹⁾
1 = LOW
Brown-out Reset voltage (VBOR) set to lower trip point level
0 = HIGH Brown-out Reset voltage (VBOR) set to higher trip point level
The higher voltage setting is recommended for operation at or above 16 MHz.
Unimplemented: Read as ‘1’
BOREN<1:0>: Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
11 = ON
Brown-out Reset is enabled; SBOREN bit is ignored
10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored
01 = SBOREN Brown-out Reset is enabled according to SBOREN
00 = OFF Brown-out Reset is disabled
LPBOREN: Low-power BOR enable bit
1=
LPBOR disabled
0=
LPBOR enabled
Unimplemented: Read as ‘1’
PWRTE: Power-up Timer Enable bit
1 = OFF PWRT is disabled
0 = ON
PWRT is enabled
MCLRE: Master Clear (MCLR) Enable bit
If LVP = 1:
RA3 pin function is MCLR.
If LVP = 0:
1 = ON
MCLR pin is MCLR.
0 = OFF MCLR pin function is port-defined function.
Note 1:
2:
See VBOR parameter for specific trip point voltages.
The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
For normal device operation, this bit should be maintained as a ‘1’.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 93