PIC16LF18854 Datasheet, PDF (172/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
10.4.3 NVMREG WRITE TO EEPROM
Writing to the EEPROM is accomplished by the
following steps:
1. Set the NVMREGS and WREN bits of the
NVMCON1 register.
2. Write the desired address (address + 7000h)
into the NVMADRH:NVMADRL register pair
(Table 10-2).
3. Perform the unlock sequence as described in
Section 10.4.2 “NVM Unlock Sequence”.
A single EEPROM word is written with NVMDATA. The
operation includes an implicit erase cycle for that word
(it is not necessary to set the FREE bit), and requires
many instruction cycles to finish. CPU execution
continues in parallel and, when complete, WR is
cleared by hardware, NVMIF is set, and an interrupt will
occur if NVMIE is also set. Software must poll the WR
bit to determine when writing is complete, or wait for the
interrupt to occur. WREN will remain unchanged.
Once the EEPROM write operation begins, clearing the
WR bit will have no effect; the operation will continue to
run to completion.
10.4.4 NVMREG ERASE OF PFM
Before writing to PFM, the word(s) to be written must
be erased or previously unwritten. PFM can only be
erased one row at a time. No automatic erase occurs
upon the initiation of the write to PFM.
To erase a PFM row:
1. Clear the NVMREGS bit of the NVMCON1
register to erase PFM locations, or set the
NMVREGS bit to erase User ID locations.
2. Write the desired address into the
NVMADRH:NVMADRL register pair (Table 10-
2).
3. Set the FREE and WREN bits of the NVMCON1
register.
4. Perform the unlock sequence as described in
Section 10.4.2 “NVM Unlock Sequence”.
If the PFM address is write-protected, the WR bit will be
cleared and the erase operation will not take place.
While erasing PFM, CPU operation is suspended, and
resumes when the operation is complete. Upon
completion, the NVMIF is set, and an interrupt will
occur if the NVMIE bit is also set.
Write latch data is not affected by erase operations,
and WREN will remain unchanged.
FIGURE 10-3:
NVM ERASE
FLOWCHART
Rev. 10-000048B
8/24/2015
Start
Erase Operation
Select Memory:
PFM, Config Words, User ID
(NVMREGS)
Select Word Address
(NVMADRH:NVMADRL)
Select Erase Operation
(FREE=1)
Enable Write/Erase Operation
(WREN=1)
Disable Interrupts
(GIE=0)
Unlock Sequence
(See Note 1)
CPU stalls while
Erase operation completes
(2 ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
Note 1: See Figure 10-2.
DS40001824A-page 172
Preliminary
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