PIC16LF18854 Datasheet, PDF (319/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
21.9 Register Definitions: ZCD Control
REGISTER 21-1: ZCDCON: ZERO-CROSS DETECTION CONTROL REGISTER
R/W-q/q
U-0
EN
—
bit 7
R-x/x
R/W-0/0
U-0
OUT
POL
—
U-0
R/W-0/0
—
INTP
R/W-0/0
INTN
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = value depends on configuration bits
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1
bit 0
EN: Zero-Cross Detection Enable bit
1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
Unimplemented: Read as ‘0’
OUT: Zero-Cross Detection Logic Level bit
POL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
POL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
POL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
Unimplemented: Read as ‘0’
INTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high ZCDx_output transition
0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition
INTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low ZCDx_output transition
0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIE3
—
—
RCIE
TXIE
BCL2IE SSP2IE
PIR3
—
—
RCIF
TXIF
BCL2IF SSP2IF
ZCDxCON
EN
—
OUT
POL
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.
BCL1IE
BCL1IF
INTP
SSP1IE
SSP1IF
INTN
Register
on page
136
145
319
TABLE 21-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE
Name Bits Bit -/7
Bit -/6
Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1
Bit 8/0
CONFIG2
Legend:
13:8 ^DEBUG
STVREN PPS1WAY
ZCDDIS
BORV
—
BOREN<1:0>
7:0 ^LPBOREN
—
—
—
PWRTE
MCLRE
WRT<1:0>
— = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.
Register
on Page
93
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 319