PIC16LF18854 Datasheet, PDF (306/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
20.13 Register Definitions: CWG Control
Long bit name prefixes for the CWG peripherals are
shown in Section 1.1 “Register and Bit naming con-
ventions”.
TABLE 20-3: LONG BIT NAMES PREFIXES
FOR CWG PERIPHERALS
Peripheral
CWG1
CWG2
CWG3
Bit Name Prefix
CWG1
CWG2
CWG3
REGISTER 20-1: CWGxCON0: CWGx CONTROL REGISTER 0
R/W-0/0 R/W/HC-0/0
U-0
U-0
U-0
R/W-0/0
EN
LD⁽¹⁾
—
—
—
bit 7
R/W-0/0
MODE<2:0>
R/W-0/0
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5-3
bit 2-0
EN: CWGx Enable bit
1 = Module is enabled
0 = Module is disabled
LD: CWGx Load Buffer bits⁽¹⁾
1 = Buffers to be loaded on the next rising/falling event
0 = Buffers not loaded
Unimplemented: Read as ‘0’
MODE<2:0>: CWGx Mode bits
111 = Reserved
110 = Reserved
101 = CWG outputs operate in Push-Pull mode
100 = CWG outputs operate in Half-Bridge mode
011 = CWG outputs operate in Reverse Full-Bridge mode
010 = CWG outputs operate in Forward Full-Bridge mode
001 = CWG outputs operate in Synchronous Steering mode
000 = CWG outputs operate in Steering mode
Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.
DS40001824A-page 306
Preliminary
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