PIC16LF18854 Datasheet, PDF (195/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 11-12: SCANLADRH: SCAN LOW ADDRESS HIGH BYTE REGISTER
R/W-0/0
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
LADR<15:8>^(1,2)
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
LADR<15:8>: Scan Start/Current Address bits^(1,2)
Most Significant bits of the current address to be fetched from, value increments on each fetch of
memory.
Note 1: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;
registers should only be read or written while SCANGO = 0 (SCANCON0 register).
2: While SCANGO = 1 (SCANCON0 register), writing to this register is ignored.
REGISTER 11-13: SCANLADRL: SCAN LOW ADDRESS LOW BYTE REGISTER
R/W-0/0
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
LADR<7:0>^(1,2)
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
LADR<7:0>: Scan Start/Current Address bits^(1,2)
Least Significant bits of the current address to be fetched from, value increments on each fetch of
memory
Note 1: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;
registers should only be read or written while SCANGO = 0 (SCANCON0 register).
2: While SCANGO = 1 (SCANCON0 register), writing to this register is ignored.
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Preliminary
DS40001824A-page 195